1. Field of the Invention
The present invention relates to the field of color television and, more particularly, to a circuit for identifying Standards in a color television set capable of receiving several Standards.
2. Discussion of the Related Art
In order to decode a video signal and to restore a color picture, a color television set must detect the transmitted TV color Standard. Present color TV sets include a system for automatically identifying the Standard that is used.
PAL and SECAM are two Standards amongst other Standards that are used. For both Standards, each line of the composite video signal includes a synchronization top, an identification burst comprising some periods of the chrominance sub-carrier signal, then the signal itself corresponding to the picture, including the superposition of luminance information and chrominance information, the chrominance information being carried by the luminance signal.
The characteristic features of the chrominance sub-carrier in the various PAL, SECAM and other Standards are defined in published documents relating to those Standards, and will not be described in detail here. However, the main characteristics of the PAL and SECAM Standards will be briefly described because these indications are useful for a better understanding of the invention.
In the PAL Standard, the frequency of the chrominance sub-carrier is the same for all the lines. For the identification bursts, the phase of the modulation vector oscillates between +135.degree. and -135.degree. from one line to the next one. The frequency of the chrominance sub-carrier is standardized at 4.43 MHz.
In the SECAM Standard, two frequencies of the chrominance sub-carrier that alternate from one line to the next one between 4.25 MHz and 4.40 MHz, are used. Those two chrominance sub-carriers are frequency modulated.
Present multi-Standard televisions must internally include distinct systems operable for decoding the luminance and chrominance signals for each Standard used. The televisions must therefore previously identify the received Standard.
FIG. 1 schematically shows a conventional circuit for identifying the PAL Standard. This circuit includes a phase comparator 10 providing a signal P active if the phase difference between two input signals of the comparator is positive, or a signal N active if the phase difference is negative. Comparator 10 receives at a first input the above-mentioned bursts at the 4.43 -MHz frequency of the sub-carrier. The second inputs of comparator 10 receives a signal Fp at the sub-carrier frequency through a circuit 12 providing to signal Fp a +90.degree. or -90.degree. phase. The selection of the +90.degree. or -90.degree. phase is determined by the state of a flip-flop 14 (FF) clocked by a signal Fh having a frequency equal to the line frequency. The role of flip-flop 14 will be understood later on.
Signal P indicating the positive sign (+90.degree.) controls a current source Ic connected to a supply voltage Vcc. Signal N indicating the negative sign (-90.degree.) controls a current source Id serially connected between the source Ic and ground. Sources Ic and Id provide equal currents. The junction between sources Ic and Id is connected to a terminal A of a capacitor C having its second terminal connected to ground. In the absence of control of one of sources Ic and Id, the voltage across capacitor C is pulled up to a value Vref=Vcc/2 through a connection of resistors R1 and R2. VA is the voltage at terminal A and across capacitor C.
Signals P and N are significant only during the bursts that occur, as above indicated, at the beginning of each line during short time periods (approximately 4 ms for a 64-ms line period). To take this situation into account, current sources Ic and Id are enabled by a window signal BG that is active only during each burst period.
With this configuration, capacitor C is charged or discharged by a constant value during each burst depending on whether signal P or signal N, respectively, is enabled. Resistors R1 and R2 have a high value in order not to substantially impair charging of capacitor C from one burst to the next one.
The elements of FIG. 1 not yet described will be explained later on.
FIG. 2 schematically shows the elements, that differ from FIG. 1, of a conventional circuit operable for identifying the SECAM Standard. Flip-flop 14 is in the present example connected to the phase comparator 10 in a configuration where the state of the flip-flop determines whether the indication of the sign provided by the phase comparator 10 is inverted or not with respect to the result of the comparison. A first input of comparator 10 receives the bursts. The second input of comparator 10 is connected to ground through a capacitor C1 and an inductance L1 that are parallel connected, and to the first input through a capacitor Cs. The resonance frequency of circuit L1C1 is set at an intermediate frequency between the red sub-carrier frequency and the blue sub-carrier frequency. The other elements (not shown) of the circuit operable for identifying the SECAM Standard are identical to the elements of FIG. 1.
In the circuits of FIGS. 1 and 2, without taking into account the presence of flip-flop 14, the indication of the sign, provided by comparator 10, is inverted every two lines when the Standard received is the appropriate one. The purpose of flip-flop 14, whose state switches at each line, is to ensure that comparator 10 provides a constant indication on the polarity sign from one line to the next one when the Standard received is the appropriate one.
FIG. 3A shows the voltage VA across capacitor C over time when the Standard received by one of the circuits of FIGS. 1 and 2 is the appropriate one. Depending on the initial state of flip-flop 14, voltage VA varies in a constant direction by steps occurring successively at the line frequency, either by increasing from value Vref (shown in solid lines), or by decreasing from value Vref (shown in dashed lines). The transition phases from one step to the next one correspond to the charging or discharging phases of capacitor C during the occurrence of bursts. To identify the received Standard, it is only necessary to detect that voltage VA reaches a high threshold value Vref+Vt or a low threshold value Vref-Vt. If the received Standard is inappropriate, voltage VA randomly oscillates about value Vref and, theoretically, does not reach the threshold voltages Vref+Vt and Vref-Vt.
In a specific implementation of the identification circuit, it is tried to obtain charging of capacitor C when the received Standard is appropriate. In this case, when the initial state of flip-flop 14 is erroneous, that is, when capacitor C starts discharging when the received Standard is appropriate, the state of flip-flop 14 must be inverted in order to invert the polarity of the sign indication (P, N) provided by the phase comparator 10. As shown in FIG. 1, the inversion is made with a comparator 16 that provides a reset signal R to flip-flop 14 when the voltage across capacitor C reaches the low threshold value Vref-Vt.
FIG. 3B shows the voltage VA over time, in the above example, when the received Standard is appropriate. The initial state of flip-flop 14 is erroneous. Voltage VA starts gradually decreasing. At a time t1, voltage VA drops below the low threshold voltage Vref-Vt and the reset signal R of flip-flop 14 is enabled. As long as signal R is enabled, flip-flop 14 remains in its last state, which is equivalent to an inversion of the state of the flip-flop during the next transition phase starting at a time t2. From time t2, voltage VA increases and passes over the threshold voltage Vref-Vt; signal R is disabled. Then, voltage VA starts gradually increasing to finally reach the high threshold voltage Vref+Vt, which is detected by a comparator 18. Then, comparator 18 indicates that the received Standard is identified.
The invention, as will be seen subsequently, only applies to such an identification circuit having a single detection threshold (Vref+Vt).
The actual operation of the circuits of FIGS. 1 and 2 is not ideal. In fact, each of these circuits can detect an inappropriate Standard as being appropriate because of the presence of noise in the received signals and parasitic phase variation phenomena. Such random phenomena cause, over a long period of time, as many positive sign indications as negative sign indications at the output of comparator 10. However, over a short period of time, there may appear a sufficient number of positive indications with respect to negative indications so that the voltage across capacitor C reaches the detection threshold Vref+Vt, which causes an erroneous detection.
One solution to avoid this problem is to increase the period preceding the detection phase by slowing down the progression of voltage VA. This is accomplished by decreasing the value of currents Ic and Id or the value of the pull-back resistors R1 and R2. However, this solution decreases the sensitivity of the identification circuit, and the Standard of very noisy signals can no longer be identified. The presence of noise causes, even if the received Standard is the appropriate one, the occurrence, from time to time, of signs having an erroneous polarity. These parasitic indications may prevent voltage VA from reaching the detection threshold, more particularly if the progression of voltage VA is slowed down.
An alternative solution is to connect in parallel several identification circuits operating according to different detection criteria. Such a solution is complex.
A further solution is, prior to selecting a Standard, to check the indications of the various Standard identification circuits and to resume an identification phase (that is, pulling-back the voltage across capacitor C to value Vref), until a single identification circuit indicates a detection. Such a method is time-consuming: an identification phase is carried out over approximately two frames.